The present invention relates to a method of manufacturing integrated circuit devices. In particular, it relates to a method of forming polycrystalline silicon lines and vias on a patterned substrate.
In the manufacture of integrated circuit devices, polycrystalline silicon is often used to form conductive lines of the type required for interconnects and for the gates of MOS transistors. While photolithography steps are usually required to define areas where such lines will be formed, it is desirable to minimize lithographic steps during semiconductor manufacture.